Switch-level Differential Fault Simulation of MOS VLSI Circuits

PARALLEL SWITCH-LEVEL SIMULATION of VLSI CIRCUITS

An evaluation of the chandy-misra-bryant algorithm for digital logic simulation. 26] Christian Sporrer and Herbert Bauer. Corolla partitioning for distributed logic simulation of vlsi-circuits. 19 Figure 14 summarizes the best speedups obtained using the conservative and optimistic protocols. Both the protocols yield relatively good speedups for the combinational circuits. The main reason for t...

The complexity of fault detection in MOS VLSI circuits

This paper considers the fault detection problem for a single fault in a single MOS channel-connected subcircuit. We identify the following three decision sub-problems : (i) decide if a test vector exists; (ii) decide if an initializing vector exists; and (iii) decide if a test pair is robust. We prove that each of these problems is NP complete. More importantly, we prove that the rst two remai...

Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits

In this paper we present a web-based distributed fault simulation framework built with standard Java Applet/Servlet technology and the popular platform independent open source database MySQL. Fault simulation plays an important role in digital electronics design flow by creating and evaluating test patterns, identifying and locating the causes of the circuit failures. Because of the rapid incre...

Efficient VLSI Fault Simulation

Partitioning VLSI-Circuits for Parallel Simulation on Transistor Level

For parallel simulation of VLSI circuits on transistor level a sophisticated partitioning of the circuits into subcircuits is crucial. Each net connecting the subcircuits causes additional communication and computation effort. As the slave processors simulating the subcircuits advance synchronously in time, the computation effort for each subcircuit should be approximately the same. In this pap...